Highly reliable gate oxide and method of fabrication

ABSTRACT

An ultra-thin gate oxide layer of hafnium oxide (HfO 2 ) and a method of formation are disclosed. The ultra-thin gate oxide layer of hafnium oxide (HfO 2 ) is formed by a two-step process. A thin hafnium (Hf) film is first formed by thermal evaporation at a low substrate temperature, after which the thin hafnium film is radically oxidized using a krypton/oxygen (Kr/O 2 ) high-density plasma to form the ultra-thin gate oxide layer of hafnium oxide (HfO 2 ). The ultra-thin gate oxide layer of hafnium oxide (HfO 2 ) formed by the method of the present invention is thermally stable in contact with silicon and is resistive to impurity diffusion at the HfO 2 /silicon interface. The formation of the ultra-thin gate oxide layer of hafnium oxide (HfO 2 ) eliminates the need for a diffusion barrier layer, allows thickness uniformity of the field oxide on the isolation regions and, more importantly, preserves the atomically smooth surface of the silicon substrate.

BACKGROUND OF THE INVENTION

[0001] The present invention relates generally to semiconductor devicesand, in particular, to ultra-thin gate oxide memory devices.

BRIEF SUMMARY OF THE INVENTION

[0002] A conventional metal-oxide-semiconductor (MOS) device isillustrated in FIG. 1. The device generally includes a gate electrode 20which acts as a conductor to which an input signal is typically appliedvia a gate terminal (not shown). Conventionally doped active areas 14and 16 are formed within the semiconductor substrate 10 and act assource and drain regions 14 and 16, respectively. A channel region 12 isformed in the semiconductor substrate 10 beneath the gate electrode 20and separates the source/drain regions 14, 16. The channel region 12 istypically doped with a dopant opposite to that of the doped source/drainregions 14, 16. The gate electrode 20 is separated from thesemiconductor substrate 10 by an insulating gate oxide layer 18, whichis typically an oxide of silicon, for example silicon dioxide (SiO₂).The gate oxide layer 18 prevents current from flowing between the gateelectrode 20 and the semiconductor source region 14, the drain region 16and/or the channel region 12.

[0003] When an input voltage is applied to the gate electrode 20, atransverse electrical field is set up in the channel region 12. Byvarying the transverse electrical field, the conductance of the channelregion 12 between the source region 14 and the drain region 16 ismodulated. This way, an electric field controls the current flow throughthe channel region 12. This type of device is commonly known as an MOSfield-effect-transistor (MOSFET).

[0004] The growth of the gate oxide layer, such as the gate oxide layer18 of FIG. 1, is a critical step in manufacturing miniaturizedsemiconductor devices. Thin gate oxide layers free of defects and ofhigh quality without contamination are essential for proper deviceoperation, especially when current design rules demand gate oxide layerswith thicknesses of less than 15 Angstroms, and even less than 10Angstroms. To obtain high-quality gate oxide layers, the surface of theactive area of the device is typically treated with a wet etch to removeany residual oxide. The gate oxide is then grown slowly, typicallythrough dry oxidation in a chlorine ambient. At this point, it isextremely important to carefully control the growth of the gate oxidebecause the thickness and uniformity of the gate oxide layer cansignificantly impact the overall operation of the device formed. Becausethe drain current in a MOS device is inversely proportional to thethickness of the gate oxide, it is desirable to make the gate oxide asthin as possible while taking into account the oxide breakdown andreliability considerations of the process. Furthermore, the use ofsilicon dioxide for gate oxide layers thinner than 20 Angstroms posesvarious problems, one of them being the leakage current caused by directtunneling, which further affects the operation of the device.

[0005] High-dielectric constant insulating materials have been proposedas gate oxide layers, but with limited results. FIG. 2 illustrates ahigh-dielectric constant insulating layer 19 formed between the gateelectrode 20 and the semiconductor substrate 10. Conventionalhigh-dielectric constant insulating materials such as tantalum oxide(Ta₂O₅), titanium oxide (TiO₂) or barium oxide (BaO), for example, arenot thermally stable when in direct contact with a silicon substrate.Accordingly, these high-dielectric constant insulating materials requirea diffusion barrier layer 21 (FIG. 2) at the interface with the siliconsubstrate, the formation of which adds process complexity.

[0006] Furthermore, using a diffusion barrier layer defeats the purposesof using a high-dielectric constant insulating material because the gatecapacitance is decreased rather than increased. If the gate structure ofFIG. 2 is viewed as a series of stacked capacitors 25 (FIG. 3), whichhas layers of thicknesses comparable to those of the gate structure ofFIG. 2, then, a first capacitor Cl (FIG. 3) corresponds to thehigh-dielectric constant insulating layer 19 and a second capacitor C₂(FIG. 3) corresponds to the diffusion barrier layer 21. The diffusionbarrier layer 21 (FIG. 2) acts as a series capacitor the addition ofwhich decreases the capacitance of the gate electrode 20. Thecapacitance of the first capacitor C₁ is larger than the capacitance ofthe second capacitor C₂ and, thus, voltage V₁ which occurs across thefirst capacitor C₁ is smaller than voltage V₂ which occurs across thesecond capacitor C₂. As a result, the applied voltage V that occursacross the series capacitors 25, that is the sum of V₁ and V₂, appearsmostly across the diffusion barrier layer 21 rather than across thehigh-dielectric constant insulating layer 19.

[0007] Accordingly, there is a need for an improved memory device whicheliminates the problems posed by the use of a conventionalhigh-dielectric constant insulating materials as gate oxide layers.There is also a need for an improved ultra-thin gate oxide layer whichis thermally stable when in contact with silicon and which is resistiveto impurity diffusion, and a novel method for its fabrication. A memorydevice with a minimal voltage drop across the gate electrode is alsodesirable, as well as a method of forming such a memory device.

SUMMARY OF THE INVENTION

[0008] The present invention provides an ultra-thin gate oxide layer ofhafnium oxide (HfO₂) as a thin medium-dielectric constant gateinsulating layer. The ultra-thin gate oxide layer of hafnium oxide(HfO₂) is formed by a two-step process: (1) a thin hafnium (Hf) film isformed by thermal evaporation at a low substrate temperature, afterwhich (2) the thin hafnium film is radically oxidized using akrypton/oxygen (Kr/O₂) high-density plasma to form the ultra-thin gateoxide layer of hafnium oxide (HfO₂). The ultra-thin gate oxide layer ofhafnium oxide (HfO₂) formed by the method of the present invention isthermally stable in contact with silicon and is resistive to impuritydiffusion at the HfO₂/silicon interface. The formation of the ultra-thingate oxide layer of hafnium oxide (HfO₂) eliminates the need for adiffusion barrier layer, allows thickness uniformity of the field oxideon the isolation regions and, more importantly, preserves the atomicallysmooth surface of the silicon substrate.

[0009] These and other advantages and features of the invention will bemore clearly understood from the following detailed description which isprovided in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 illustrates a schematic cross-sectional view of a portionof a conventional MOS device formed in accordance with a method of theprior art.

[0011]FIG. 2 illustrates a schematic cross-sectional view of a portionof a conventional MOS device formed in accordance with another method ofthe prior art.

[0012]FIG. 3 is a schematic view of a series of capacitors correspondingto stacked layers of the structure of FIG. 2.

[0013]FIG. 4 illustrates a schematic cross-sectional view of a portionof a memory device formed according to a method of the presentinvention.

[0014]FIG. 5 illustrates a schematic cross-sectional view of the memorydevice of FIG. 4 at a stage of processing subsequent to that shown inFIG. 4.

[0015]FIG. 6 illustrates a schematic cross-sectional view of the memorydevice of FIG. 4 at a stage of processing subsequent to that shown inFIG. 5.

[0016]FIG. 7 illustrates a schematic cross-sectional view of the memorydevice of FIG. 4 at a stage of processing subsequent to that shown inFIG. 6.

[0017]FIG. 8 illustrates a schematic cross-sectional view of the memorydevice of FIG. 4 at a stage of processing subsequent to that shown inFIG. 7.

[0018]FIG. 9 illustrates a schematic cross-sectional view of the memorydevice of FIG. 4 at a stage of processing subsequent to that shown inFIG. 8.

[0019]FIG. 10 illustrates a schematic cross-sectional view of the memorydevice of FIG. 4 at a stage of processing subsequent to that shown inFIG. 9.

[0020]FIG. 11 illustrates a schematic cross-sectional view of the memorydevice of FIG. 4 at a stage of processing subsequent to that shown inFIG. 10.

[0021]FIG. 12 illustrates a schematic cross-sectional view of the memorydevice of FIG. 4 at a stage of processing subsequent to that shown inFIG. 11.

[0022]FIG. 13 illustrates a schematic cross-sectional view of the memorydevice of FIG. 4 at a stage of processing subsequent to that shown inFIG. 12.

[0023]FIG. 14 illustrates a computer system having a memory cell with agate stack including the ultra-thin gate oxide layer of hafnium oxide(HfO₂) formed according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0024] In the following detailed description, reference is made tovarious specific embodiments in which the invention may be practiced.These embodiments are described with sufficient detail to enable thoseskilled in the art to practice the invention, and it is to be understoodthat other embodiments may be employed, and that various structural,logical, and electrical changes may be made without departing from thespirit or scope of the invention.

[0025] The term “substrate” used in the following description mayinclude any semiconductor-based structure that has an exposed substratesurface. Structure must be understood to include silicon-on insulator(SOI), silicon-on sapphire (SOS), doped and undoped semiconductors,epitaxial layers of silicon supported by a base semiconductorfoundation, and other semiconductor structures. When reference is madeto a substrate or wafer in the following description, previous processsteps may have been utilized to form regions or junctions in or over thebase semiconductor or foundation.

[0026] The term “hafnium” is intended to include not only elementalhafnium, but hafnium with other trace metals or in various alloyedcombinations with other metals as known in the semiconductor industry,as long as such hafnium alloy is conductive, and as long as the physicaland electrical properties of the hafnium remain unchanged. Similarly,the term “hafnium oxide” is intended to include not only elementalhafnium oxide, but hafnium oxide with other trace metals or in variousalloyed combinations with other metals as known in the semiconductorindustry, as long as the physical and electrical properties of thehafnium oxide remain unaltered.

[0027] The present invention provides an improved memory devicecomprising gate structures including an ultra-thin medium-dielectricconstant gate insulator formed of hafnium oxide. The ultra-thinmedium-dielectric constant gate insulator of the invention reduces thevoltage drop across the gate electrode, preserves the smoothness of thesubstrate surface and permits effective transistor operations withoutthe need of a diffusion barrier layer.

[0028] Referring now to the drawings, where like elements are designatedby like reference numerals, FIGS. 4-13 illustrate the formation of oneembodiment of an improved memory device 100 (FIG. 13) of the presentinvention. FIG. 4 illustrates a semiconductor substrate 50 having a well52, which is typically doped to a predetermined conductivity, forexample P-type or N-type, depending on whether NMOS or PMOS transistorswill be formed therein. For the purposes of the present invention, thewell 52 is considered to be a P-well formed by implanting P-typeimpurity atoms, such as boron, for example, by known methods of the art.In this application, the semiconductor substrate 50 will be referred toas a P-type silicon substrate 50, but it must be understood that thesubstrate need not be silicon-based. Thus, the present invention hasequal applicability to other semiconductor substrates, such as, forexample, silicon-germanium, germanium, silicon-on-saphire, orgallium-arsenide substrates, among others.

[0029] The structure of FIG. 4 further includes isolation regions 53,which, as known in the art, may be field oxide (FOX) regions formed by ashallow trenches for isolation (STI) process, for example. In anexemplary embodiment, the isolation regions 53 are shallow trenches forisolation filled with high density plasma (HDP) oxide, a material whichhas a high ability to effectively fill narrow trenches. Alternatively,an insulating layer (not shown) formed of an oxide or of siliconnitride, for example, may be formed on the trench sidewalls, prior tofilling the trenches with the isolation dielectric, to aid in smoothingout the corners in the bottom of the trenches and to reduce the amountof stress in the dielectric used to later fill in the trenches.

[0030] Subsequent to the formation of the isolation regions 53 (FIG. 4),an ultra-thin layer of insulating material 60 of hafnium (Hf) is formedover the silicon substrate 50 including the isolation regions 53, asshown in FIG. 5. Hafnium is the preferred material for the insulatingmaterial 60 because, as it will be explained in more detail below,hafnium forms the most stable oxide with the highest heat of formation(ΔHf=271 Kcal/mol) among the elements of group IVA of the periodic table(Ti, Zr, Hf). Hafnium can also reduce the native silicon dioxide (SiO₂)layer to form hafnium oxide (HfO₂). Hafnium is further preferred becausehafnium oxide (HfO₂) has a medium-dielectric constant (k) of about 30with a bandgap of 5.68 eV. Hafnium oxide (HfO₂) is very resistive toimpurity diffusion and intermixing at the interface HfO₂/silicon becauseof its high density, which is of about 9.69 g/cm³.

[0031] In a preferred embodiment of the invention, the ultra-thinhafnium layer 60 (FIG. 5) is formed by thermal evaporation, for exampleby electron-beam evaporation, using an ultra-high purity Hf metal slug,of about 99,9999% purity, and at a low temperature substrate of about150° C. to about 200° C. The ultra-thin hafnium layer 60 is formed overthe whole surface of the silicon substrate 50, including the isolationregions 53, to a thickness of about 10 Angstroms to about 100 Angstroms,more preferably of about 10 Angstroms to about 50 Angstroms.

[0032] The formation of the ultra-thin hafnium layer 60 (FIG. 5) by amethod of the present invention has advantages over conventionaldeposition techniques. Conventional hafnium metal deposition processesof the prior art include reactive sputtering, such as magnetronsputtering in an argon/oxygen ambient or in an argon ambient, duringwhich ion bombardment damages the surface of the silicon substrate. Incontrast, the formation of the ultra-thin hafnium layer 60 by thermalevaporation preserves the original atomically smooth surface of thesilicon substrate 50. Preservation of the smoothness of a siliconsurface is an important property in the semiconductor industry, as theroughness of the substrate surface has been recently related to theleakage current. In a recent article, The electronic structure of theatomic scale of ultrathin gate oxides, Nature, Vol. 399, 1999, pp.753-761, Muller et al. have emphasized that a fundamental characteristicof an ultra-thin gate oxide layer is the ability of the oxide to controlthe roughness of the oxide/silicon interface at an atomic scale. Mulleret al. have demonstrated that the leakage current through a 10 Angstromsoxide increases by about a factor of 10 for every 0.1 Angstroms increasein the root-mean-square (rms) roughness. The leakage current inconjunction with the sub-threshold leakage are the most importantcharacteristics of MOSFET devices. Thus, the method of the presentinvention for forming the ultra-thin hafnium layer 60 of FIG. 5 avoidsdamage of the silicon substrate 50, preserves the originally atomicallysmooth surface of the silicon substrate 50 and, therefore, reduces theleakage current.

[0033] Subsequent to the formation of the ultra-thin hafnium layer 60(FIG. 5), an ultra-thin hafnium gate oxide (HfO₂) layer 62 (FIG. 6) isformed by oxidation of the ultra-thin hafnium layer 60. In a preferredembodiment of the invention, the ultra-thin hafnium layer 60 is oxidizedat low temperatures by atomic oxygen generated in a high-density krypton(Kr) plasma. Precise details of a silicon oxidation technique, which canbe employed for the hafnium oxidation of the present invention, weregiven recently by Saito et al., in High-Intergity Silcion Oxide Grown atLow-Temperature by Atomic Oxygen Generated in High-Density KryptonPlasma, Extended Abstracts of the 1999 Int'l Conference on Solid StateDevices and Materials, (Tokyo, 1999), pp. 152-53, the disclosure ofwhich is incorporated by reference herein. However, a brief summary ofhow an ultra-thin gate oxide layer is formed by atomic oxygen generatedin a high-density krypton (Kr) plasma is believed to be helpful to theunderstanding of the present invention.

[0034] As Saito et al. have reported, silicon dioxide films were grownby direct oxidation of a silicon surface at about 400° C. and at lowelectron temperature (below 1.3 eV), low ion bombardment energy (lessthan 7 eV) and high plasma density (above 10¹²/cm³). A mixed gas ofabout 3% oxygen in krypton (O₂/Kr) was used at a pressure of 1 Torr anda microwave density of about 5 W/cm². The typical growth rate of thesilicon oxide was 14 Angstroms for about 10 minutes. In Low-TemperatureGrowth of High-Intergity Silicon Oxide Films by Oxygen Radial Generatedin High-Density Krypton Plasma, IEEE Tech. Dig., 1999, pp. 249-252,Hirayama et al. further analyzed film growth in O₂/Kr plasma anddemonstrated that the oxidation rate of O₂/Kr plasma is faster than theoxidation rate of an O₂/He plasma. Hirayama et al. also showed that thegrowth rate of O₂/Kr mixed plasma is higher than the growth rate ofthermally grown silicon oxide films at 1000° C.

[0035] In accordance with the findings of Saito et al. and Hirayama etal., the ultra-thin hafnium layer 60 (FIG. 5) undergoes oxidation in ahigh-density microwave 3% oxygen/krypton (O₂/Kr) plasma at a temperatureof about 400° C. to form the ultra-thin hafnium gate oxide (HfO₂) layer62 of FIG. 6. The ultra-thin hafnium gate oxide (HfO₂) formed by themethod of the present invention has a high growth rate, high dielectricstrength, and low interface trap and bulk charge. Furthermore, accordingto the findings of Saito et al., the ultra-thin hafnium gate oxide(HfO₂) can displace native thermally grown silicon dioxide.

[0036] Another advantage of using the oxygen/krypton (O₂/Kr) plasma forthe oxidation of the ultra-thin hafnium layer 60 of FIG. 5 is that thethickness variation of the ultra-thin hafnium gate oxide (HfO₂) layer 62(FIG. 6) at the edges of the isolation regions 53 (FIG. 6) isdramatically improved compared with the thickness variation ofconventional thermal oxidation processes. This is because the oxidegrowth in an oxygen/krypton (O₂/Kr) plasma does not depend on surfaceorientation and oxygen radicals can penetrate any place, even verycomplicated structures, due to their very small atomic radius. Thesefindings have been reported by Saito et al. in Advantage of RadicalOxidation for Improving Reliability of Ultra-Thin Gate Oxide, VLSI Tech.Dig., (2000 Symposium on VLSI Technology Digest of Technical Papers),2000, pp. 176-77, the disclosure of which is incorporated by referenceherein. Accordingly, the radical oxidation of the ultrathin hafniumlayer 60 of FIG. 5 may be conducted on a silicon surface of anyorientation, for example on a silicon surface of <111> orientation, andthe invention is not limited to a silicon surface of <100> orientationwhich is characteristic to the thermal oxidation processes of the priorart.

[0037] After the formation of the ultra-thin hafnium gate oxide (HfO₂)layer 62 (FIG. 6), a conductive layer 64 is formed over the ultra-thinhafnium gate oxide (HfO₂) layer 62, as shown in FIG. 7. The conductivelayer 64 may be formed, for example, of doped polysilicon, metals, metalsilicides, conductive metal oxides, or combinations of conductivematerials, for example, a refractory metal silicide layer overlying adoped polysilicon layer. In any event, the ultra-thin hafnium gate oxide(HfO₂) layer 62 acts as an impurity diffusion barrier layer which allowsthe fabrication of the gate structures 70 (FIG. 11) without thedepletion effect.

[0038] In an exemplary embodiment of the invention, the conductive layer64 is formed of polysilicon, which may be deposited over the ultra-thinhafnium gate oxide (HfO₂) layer 62 via LPCVD procedures, at atemperature of about 300° C. to about 700° C., and to a thickness ofabout 100 Angstroms to about 2,000 Angstroms. The polysilicon layer 64may be doped in situ during deposition with arsine or phosphine in asilane ambient, or the polysilicon layer 64 may be depositedintrinsically and then doped by ion implantation of arsenic orphosphorous ions. After its deposition, the polysilicon layer 64 may beplanarized by chemical mechanical polishing (CMP), for example, butother suitable methods could be used also, as desired. In any event, theformation of the ultra-thin hafnium gate oxide (HfO₂) layer 62 by themethod of the present invention eliminates the need for an additionalbarrier layer between the ultra-thin hafnium gate oxide (HfO₂) layer 62and the polysilicon layer 64 to prevent reaction between the polysiliconand the hafnium oxide.

[0039] In an exemplary embodiment of the invention, silicide regions 65may be formed over the polysilicon layer 64, as illustrated in FIG. 8.If the silicide regions are desired, a layer of metal capable of forminga silicide (not shown) may be deposited over the polysilicon layer 64(FIG. 7) by sputtering by RF or DC or by other similar methods such asCVD, to a thickness of about 200 Angstroms to about 500 Angstroms.Subsequent to the deposition of the metal capable of forming a silicide,the silicon substrate 50 undergoes a rapid thermal anneal (RTA),typically for about 10 to 60 seconds, using a nitrogen ambient, at about600° C. to about 850° C. so that the metal in direct contact with thepolysilicon layer 64 is converted to its silicide. As shown in FIG. 8,silicide layer 65 forms a conductive region on top of the polysiliconlayer 64. Preferably, the refractory metal has low resistance and lowresistivity as a silicide. However, the refractory metal silicide maycomprise any refractory metal, including but not limiting to titanium,cobalt, tungsten, tantalum, molybdenum, and platinum.

[0040] Although the following processing steps for the completion of thegate stacks 70 (FIG. 11) will refer to and illustrate the silicide layer65 formed over the polysilicon layer 64, it must be understood that thepresent invention is not limited to this embodiment, and otherembodiments such as the formation of gate stacks without a silicidelayer on the polysilicon gate, are also contemplated. A protective capmaterial 66 is formed over the silicide layer 65 as shown in FIG. 8. Thecap material may be formed of silicon dielectrics such as siliconnitride or silicon oxide, but TEOS or carbides may be used also. The capmaterial 66 may be formed via PECVD deposition procedures, for example,at a temperature between about 300° C. to about 600° C., to a thicknessof about 500 Angstroms to about 2,000 Angstroms.

[0041] Next, the structure of FIG. 8 is patterned using a photoresistlayer 67 (FIG. 9) formed over the cap material 66 to a thickness ofabout 1,000 Angstroms to about 10,000 Angstroms. The photoresist layer67 is patterned with a mask (not shown) and the ultra-thin hafnium gateoxide (HfO₂) layer 62, the polysilicon layer 64, the silicide layer 65and the cap material 66 are anisotropically etched through the patternedphotoresist to obtain a plurality of polysilicon gates 70 a having ontop portions 67 a of the photoresist layer, as shown in FIG. 10.Subsequent to the formation of the polysilicon gates 70 a, the topportions 67 a of the photoresist layer are removed by conventionaltechniques, such as oxygen plasma, for example, or by flooding thesilicon substrate 50 with UV irradiation to degrade portions 67 a of thephotoresist layer and obtain gate stacks 70 of FIG. 11.

[0042] As illustrated in FIG. 11, each of the gate stacks 70 comprisesthe ultra-thin hafnium gate oxide (HfO₂) layer 62, the polysilicon layer64, the silicide layer 65 and the protective cap material 66. The gatestacks 70 may now be used in a conventional implant process where thegate stacks are needed to mask the dopant implantation of source/ drainregions 82 (FIG. 12) of the adjacent transistors defined by the gatestacks. As such, FIG. 11 illustrates the formation of lightly dopeddrain (LDD) regions 72 in the silicon substrate 50. As known in the art,the LDD regions 72 may be formed by implanting low dosages ofconductivity-altering dopants with an LDD mask (not shown) or using thegate stacks 70 as an implantation mask. Thus, in the P-well 52 of thesilicon substrate 50, N-type dopants such as arsenic or phosphorous maybe implanted at a low energy dose, for example of about 1×10¹⁵atoms/cm², using the gate stacks 70 as a mask.

[0043] The next step in the process flow is the formation of spacers 68illustrated in FIG. 12. Spacers 68 may be formed, for example, bydepositing a silicon nitride film or a silicon oxide material over thestructure of FIG. 11 and then anisotropically etching with an RIE plasmato form the spacers 68 on each of the sidewalls of the gate stacks 70.

[0044] The gate stacks 70 protected by spacers 68 can now undergoconventional processing steps for the formation of source/drain regionsin the silicon substrate 50. As such, using the gate stacks 70 as animplantation mask, heavily doped source/drain regions 82 are formed inthe uncovered portions of the silicon substrate 50 via an ionimplantation procedure performed at an energy of about 50 KeV to about70 KeV, and at a dose of about 2×10¹⁵ to about 5×10¹⁵ atoms/cm², usingarsenic or phosphorous, for example. Thermal annealing for activationmay be carried out in a nitrogen atmosphere at about 1000° C. for about10 minutes.

[0045] Conventional processing steps can now be carried out to formconductors 89 and/or capacitors 99 with associated conductive plugs 99a, all illustrated in FIG. 13, and to complete the formation of a DRAMmemory device 100. For this, an insulating layer 97 is formed over thestructure of FIG. 12 and contact openings (not shown) are createdthrough the insulating layer 97. The insulating layer 97, may includeborophosphosilicate glass (BPSG) or phosphosilicate glass (PSG), forexample, and may be formed by normal CVD or LPCVD processes to athickness of about 1,000 Angstroms to about 5,000 Angstroms. To createcontact openings through the insulating layer 97, a photoresist material(not shown) is deposited and patterned using conventionalphotolithography steps and the insulating layer 97 is then etched, by awet etch for example, so that the contact openings extend tosource/drain regions 82. Conductors 89 and/or associated conductiveplugs 99 a of capacitors 99 are then formed by known metallizationprocesses.

[0046] The gate stacks 70 including the ultra-thin hafnium gate oxide(HfO₂) layer 62 formed in accordance with embodiments of the presentinvention could be used in any integrated circuit structure such as in aprocessor-based system 400 (FIG. 14) which includes a memory circuit448, for example a memory module containing a plurality of DRAM memorydevices 100 having gate stacks comprising the ultra-thin hafnium gateoxide (HfO₂) layer 62 formed according to the present invention. Aprocessor system, such as a computer system, generally comprises acentral processing unit (CPU) 444, such as a microprocessor, a digitalsignal processor, or other programmable digital logic devices, whichcommunicates with an input/output (I/O) device 446 over a bus 452. Thememory 448 communicates with the system over bus 452. The processingunit 444 and other devices illustrated in FIG. 14 may also containcircuits having transistors with gate stacks comprising the ultra-thinhafnium gate oxide (HfO₂) layer 62 formed according to the presentinvention.

[0047] Although the invention has been illustrated for a DRAM memorydevice, such as the DRAM memory device 100 (FIG. 13), fabricated on ap-type substrate, the invention could also be fabricated on an n-typesubstrate, as well-known in the art. This, of course, will change thedoping and conductivity of the operative layers in the fabricateddevice.

[0048] The above description and drawings are only to be- consideredillustrative of exemplary embodiments which achieve the features andadvantages of the present invention. Modification and substitutions tospecific process conditions and structures can be made without departingfrom the spirit and scope of the present invention. Accordingly, theinvention is not to be considered as being limited by the foregoingdescription and drawings, but is only limited by the scope of theappended claims.

What is claimed as new and desired to be protected by letters patent ofthe united states is:
 1. A transistor comprising: source and drainregions provided in a semiconductor substrate; and a gate structure onsaid semiconductor substrate between said source and drain regions, saidgate structure comprising a hafnium oxide layer overlying saidsemiconductor substrate and a conductive layer overlying said hafniumoxide layer.
 2. The transistor of claim 1, wherein said hafnium oxidelayer has a thickness of about 10 Angstroms to about 100 Angstroms. 3.The transistor of claim 2, wherein said hafnium oxide layer has athickness of about 10 Angstroms to about 50 Angstroms.
 4. The transistorof claim 1, wherein said conductive layer is formed of a materialselected from the group consisting of metals, metal silicides,polysilicon and metal oxides.
 5. The transistor of claim 1, wherein saidsemiconductor substrate is a silicon substrate.
 6. The transistor ofclaim 5, wherein said silicon substrate has a surface of <100>orientation, said surface being adjacent to said hafnium oxide layer. 7.The transistor of claim 5, wherein said silicon substrate has a surfaceof <111> orientation, said surface being adjacent to said hafnium oxidelayer.
 8. The transistor of claim 1 further comprising a silicide layeroverlying said conductive layer.
 9. A memory device comprising: asemiconductor substrate; a memory cell access transistor comprising: agate stack fabricated on said semiconductor substrate, said gate stackincluding a hafnium oxide layer overlying said semiconductor substrateand a conductive layer overlying said hafnium oxide layer; and sourceand drain regions formed in said semiconductor substrate disposedadjacent to said gate stack.
 10. The memory device of claim 9, whereinsaid hafnium oxide layer has a thickness of about 10 Angstroms to about100 Angstroms.
 11. The memory device of claim 10, wherein said hafniumoxide layer has a thickness of about 10 Angstroms to about 50 Angstroms.12. The memory device of claim 9, wherein said conductive layer isformed of a material selected from the group consisting of metals, metalsilicides, polysilicon and metal oxides.
 13. The memory device of claim9, wherein said semiconductor substrate is a silicon substrate.
 14. Thememory device of claim 13, wherein said silicon substrate has a surfaceof <100> orientation, said surface being adjacent to said hafnium oxidelayer.
 15. The memory device of claim 13, wherein said silicon substratehas a surface of <111> orientation, said surface being adjacent to saidhafnium oxide layer.
 16. The memory device of claim 9 further comprisinga silicide layer overlying said conductive layer.
 17. A processor-basedsystem comprising: a processor; and an integrated circuit coupled tosaid processor, at least one of said integrated circuit and processorcomprising a transistor, said transistor comprising: source and drainregions provided in a semiconductor substrate; and a gate stackfabricated on said semiconductor substrate, said gate stack including ahafnium oxide layer overlying said semiconductor substrate and aconductive layer overlying said hafnium oxide layer.
 18. Theprocessor-based system of claim 17, wherein said hafnium oxide layer hasa thickness of about 10 Angstroms to about 100 Angstroms.
 19. Theprocessor-based system of claim 18, wherein said hafnium oxide layer hasa thickness of about 10 Angstroms to about 50 Angstroms.
 20. Theprocessor-based system of claim 17, wherein-said conductive layer isformed of a material selected from the group consisting of metals, metalsilicides, polysilicon and metal oxides.
 21. The processor-based systemof claim 17, wherein said semiconductor substrate is a siliconsubstrate.
 22. The processor-based system of claim 21, wherein saidsilicon substrate has a surface of <100> orientation, said surface beingadjacent to said hafnium oxide layer.
 23. The processor-based system ofclaim 21, wherein said silicon substrate has a surface of <111>orientation, said surface being adjacent to said hafnium oxide layer.24. The processor-based system of claim 17 further comprising a silicidelayer overlying said conductive layer.
 25. A method for forming a gatestructure for a semiconductor device comprising the steps of: forming ahafnium layer on a semiconductor substrate; converting said hafniumlayer to a hafnium oxide layer; and forming a conductive layer over saidhafnium oxide layer.
 26. The method of claim 25, wherein said hafniumlayer is formed by thermal evaporation.
 27. The method of claim 26,wherein said hafnium layer is formed by electron beam evaporation. 28.The method of claim 26, wherein said hafnium layer is formed at atemperature of about 150° C. to about 200° C.
 29. The method of claim26, wherein said hafnium layer is formed to a thickness of about 10Angstroms to about 100 Angstroms.
 30. The method of claim 29, whereinsaid hafnium layer is formed to a thickness of about 10 Angstroms toabout 50 Angstroms.
 31. The method of claim 27, wherein said hafniumoxide layer is formed by oxidizing said hafnium layer.
 32. The method ofclaim 31, wherein said hafnium oxide layer is formed by oxidizing saidhafnium layer with atomic oxygen.
 33. The method of claim 32, whereinsaid hafnium oxide layer is formed by oxidizing said hafnium layer witha high-density krypton plasma.
 34. The method of claim 33, wherein saidhafnium oxide layer is formed by oxidizing said hafnium layer with ahigh-density krypton plasma at about 400° C.
 35. The method of claim 34,wherein said hafnium oxide layer is formed by oxidizing said hafniumlayer with a high-density 3% oxygen/krypton plasma at about 400° C. 36.The method of claim 35, wherein said hafnium oxide layer is formed byoxidizing said hafnium layer with a 3% high-density oxygen/kryptonplasma at about 400° C. and at about 1 Torr.
 37. The method of claim 25,wherein said conductive layer is formed of a material selected from thegroup consisting of metals, metal silicides, polysilicon and metaloxides.
 38. The method of claim 25, wherein said semiconductor substrateis a silicon substrate.
 39. The method of claim 38, wherein said siliconsubstrate has a surface of <100> orientation, said surface beingadjacent to said hafnium oxide layer.
 40. The method of claim 38,wherein said silicon substrate has a surface of <111> orientation, saidsurface being adjacent to said hafnium oxide layer.
 41. The method ofclaim 25 further comprising forming a silicide layer overlying saidconductive layer.
 42. The method of claim 41 further comprising forminga cap layer overlying said silicide layer.
 43. A method of forming amemory cell comprising the steps of: forming at least one gate stackover a substrate, said gate stack comprising a hafnium oxide layer ofabout 10 Angstroms to about 100 Angstroms thick and a conductive layerover said hafnium oxide layer; forming source and drain regions in saidsubstrate on opposite sides of each of said plurality of gate stacks;and forming a storage device connected to one of said source and drainregions.
 44. The method of claim 43, wherein said hafnium oxide layer isformed by oxidizing a hafnium layer formed over said substrate.
 45. Themethod of claim 44, wherein said hafnium layer is formed by thermalevaporation.
 46. The method of claim 45, wherein said hafnium layer isformed by electron beam evaporation.
 47. The method of claim 46, whereinsaid hafnium layer is formed at a temperature of about 150° C. to about200° C.
 48. The method of claim 47, wherein said hafnium layer is formedto a thickness of about 10 Angstroms to about 100 Angstroms.
 49. Themethod of claim 48, wherein said hafnium layer is formed to a thicknessof about 10 Angstroms to about 50 Angstroms.
 50. The method of claim 44,wherein said hafnium oxide layer is formed by oxidizing said hafniumlayer with atomic oxygen.
 51. The method of claim 50, wherein saidhafnium oxide layer is formed by oxidizing said hafnium layer with ahigh-density krypton plasma.
 52. The method of claim 51, wherein saidhafnium oxide layer is formed by oxidizing said hafnium layer with ahigh-density krypton plasma at about 400° C.
 53. The method of claim 52,wherein said hafnium oxide layer is formed by oxidizing said hafniumlayer with a high-density 3% oxygen/krypton plasma at about 400° C. 54.The method of claim 53, wherein said hafnium oxide layer is formed byoxidizing said hafnium layer with a 3% high-density oxygen/kryptonplasma at about 400° C. and at about 1 Torr.
 55. The method of claim 43,wherein said conductive layer is formed of a material selected from thegroup consisting of metals, metal silicides, polysilicon and metaloxides.
 56. The method of claim 43, wherein said substrate is asemiconductor substrate.
 57. The method of claim 56, wherein saidsemiconductor substrate is a silicon substrate.
 58. The method of claim57, wherein said silicon substrate has a surface of <100> orientation,said surface being adjacent to said hafnium oxide layer.
 59. The methodof claim 57, wherein said silicon substrate has a surface of <111 >orientation, said surface being adjacent to said hafnium oxide layer.60. A method of proving an oxide layer over of a surface of a siliconsubstrate comprising the steps of: thermally evaporating a hafnium layerover said surface; and oxidizing said hafnium layer with a high-densitykrypton plasma to form a hafnium oxide layer.
 61. The method of claim60, wherein said hafnium layer is formed by electron beam evaporation.62. The method of claim 61, wherein said hafnium layer is formed at atemperature of about 150° C. to about 200° C.
 63. The method of claim60, wherein said hafnium layer is formed to a thickness of about 10Angstroms to about 100 Angstroms.
 64. The method of claim 63, whereinsaid hafnium layer is formed to a thickness of about 10 Angstroms toabout 50 Angstroms.
 65. The method of claim 60, wherein said hafniumoxide layer is formed by oxidizing said hafnium layer with ahigh-density krypton plasma at about 400° C.
 66. The method of claim 65,wherein said hafnium oxide layer is formed by oxidizing said hafniumlayer with a high-density 3% oxygen/krypton plasma at about 400° C. 67.The method of claim 66, wherein said hafnium oxide layer is formed byoxidizing said hafnium layer with a 3% high-density oxygen/kryptonplasma at about 400° C. and at about 1 Torr.
 68. The method of claim 60,wherein said surface has <100> orientation.
 69. The method of claim 60,wherein said surface has <111> orientation.
 70. A method of forming agate structure for a semiconductor device comprising the steps of:thermally evaporating a hafnium layer over a surface of a siliconsubstrate at a temperature of about 150° C. to about 200° C.; oxidizingsaid hafnium layer with a high-density 3% oxygen/krypton plasma at about400° C. and at about 1 Torr to form a hafnium oxide layer; and forming aconductive layer over said hafnium oxide layer.
 71. A method of provinga hafnium oxide layer having a thickness of about 10 Angstroms over of asurface of a silicon substrate comprising the steps of: thermallyevaporating a hafnium layer over said surface at a temperature of about150° C. to about 200° C.; and oxidizing said hafnium layer with ahigh-density 3% oxygen/krypton plasma at about 400° C. and at about 1Torr to form said hafnium oxide layer.